1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) which includes thin film transistors (TFTs) and to a method of manufacturing the same and more specifically, to a method of manufacturing LCDs which has a reduced number of masking steps.
2. Description of the Related Art
Among display devices for showing visual images on a screen, thin film flat panel display devices are highly favored because of their light weight and easy adaptability. Recent research activities have focused on the development of liquid crystal display devices because of their high resolution and fast response time suitable for display of motion picture images.
A liquid crystal display device works by using polarization and optical anisotropy of a liquid crystal. By controlling the orientation of rod-shaped liquid crystal molecules via a polarization technique, transmission and interception of a light through the liquid crystal molecules are achieved due to the anisotropy of the liquid crystal. This principle is utilized in liquid crystal display devices. Active matrix liquid crystal displays (or AMLCDs) having TFTs arranged in a matrix pattern and pixel electrodes connected to the TFTs provide high quality images and are now widely used. An active panel of a conventional LCD will now be described with reference to FIG. 1.
The conventional LCD comprises two panels 3 and 5 on which a plurality of elements are placed, and liquid crystal (not shown) is located between the two panels 3, 5. One panel of the LCD includes elements reproducing colors, which panel is called a color filter panel 3. The color filter panel 3 has color filters 7 including red (R), green (G) and blue (B) filters, which are sequentially arranged on a first transparent substrate 81 and correspond to pixels formed in a matrix pattern. Among these color filters 7, black matrixes 9 are arranged in a lattice pattern so as to prevent mixture of colors at boundaries between the color filters. A common electrode 85 covers the color filters 7 and functions as one electrode for generating an electric field applied to the liquid crystal.
The other panel is an active panel 5 which includes switch elements and bus lines, which generate the electric field for driving the liquid crystal. The active panel 5 has a pixel electrode 41 which is disposed on a second transparent substrate 83. The pixel electrode 41 is located opposite to the common electrode 85 disposed on the color filter panel 3 and functions as the other electrode for generating the electric field applied to the liquid crystal. Signal bus lines 13 extend along the column direction of the array of the pixel electrodes 41 and data bus lines 23 extend along the row direction of the array of the pixel electrode 41. A TFT 89 which functions as a switch element for driving the pixel electrode 41 is formed on the substrate 83. A gate electrode 11 of the TFT 89 is connected with the signal bus line 13 ("gate bus line"), a source electrode 21 is connected with the data bus line 23 ("source bus line"). A drain electrode 31 of the TFT 89 is connected with the pixel electrode 41.
Between the source electrode 21 and the drain electrode 31, a semiconductor layer 33 is formed as seen in FIG. 2. The source electrode 21 and the drain electrode 31 are in ohmic contact with the semiconductor layer 33. A gate pad 15 and a source pad 25, which function as terminals receiving external signals, are disposed at the end portions of the gate bus line 13 and the source bus line 23, respectively. A gate pad terminal 57 and a source pad terminal 67 are formed on the gate pad 15 and the source pad 25, respectively.
When an external electric signal, which is applied to the gate pad 15, is sent to the gate electrode 11 through the gate bus line 13, electrical picture data, which is applied to the source pad 25, is sent to the source electrode 21 through the source bus line 23 and to the drain electrode 31. If the electric signal is not applied to the gate bus line 13, the drain electrode 31 is electrically isolated from the source electrode 21. Accordingly, whether the data signal is applied to the drain electrode 31 is determined by controlling the signal to the gate electrode 11. Therefore, application of the data signal to the pixel electrode 41, which is connected with the drain electrode 31, is artificially controlled. In other words, the TFT 89 functions as a switch for selectively driving the pixel electrode. A gate insulating layer 17 is formed between the gate bus line 13 and the source bus line 23 in order to electrically isolate the gate bus line 13 and the source bus line 23 and a passivation layer 37 covers the source bus line 23 in order to protect the elements as shown in FIGS. 3a-3f described below.
These two panels, i.e. the color filter panel 3 and the active panel 5, are arranged to face each other with a certain distance or "cell gap" disposed therebetween. In between the spaced panels 3, 5 in the cell gap, liquid crystal is injected. In order to keep the cell gap between the two panels 3 and 5 constant and to prevent the liquid crystal from leaking outside, the edges of the joined panels are sealed with epoxy or similar material. The liquid crystal panel is now completed as described above.
Many complicated processes for manufacturing the liquid crystal panel are required, especially, many masking processes for manufacturing the active panel including TFTs. Because the active panel includes the elements which mainly affect the performance of the LCD, it is important for manufacturing high quality LCD products to simplify the processes for manufacturing the active panel. In general, the manufacturing processes are determined by the types of materials used to form each element, the structure thereof and methods for solving the problems such as static electricity which occur during the forming processes.
Although a resistance of a material used to form gate bus lines rarely affects the picture quality when manufacturing the conventional miniature liquid crystal display device, the resistance affects the picture quality when manufacturing a large area liquid crystal display, i.e. computer monitor of 12 inches or more. In other words, a metal which has a good surface-stability when the metal is formed into a thin film, such as tantalum, tungsten and molybdenum, is used for forming gate elements (gate bus lines, gate electrodes and gate pads) of the conventional miniature LCD. For forming the gate elements of the large area LCD, a metal which has a low resistance, such as aluminum, is preferably used.
However, there are many problems with forming the gate elements of aluminum or aluminum alloy. Hillocks, which are formed on the surface of the aluminum, are the most serious problem. After depositing aluminum, minute particles of the aluminum exist on the aluminum film. During the manufacturing process, the particles are growing so much that they break an insulating layer because of a high temperature condition, resulting in the deterioration of the LCD. Furthermore, if the gate elements are formed of aluminum, the contact-resistance between the gate elements and ITO increases. In other words, Al.sub.2 O.sub.3 film is unintentionally formed between the aluminum and the ITO when the ITO is deposited on the aluminum, and consequently, the contact-resistance increases. As a result, transmission of the electric signal to the gate is significantly delayed.
In order to enhance the surface-stability of the aluminum film, the conventional art includes a step of anodizing the surface of the aluminum. When anodizing the aluminum, a portion of the aluminum, which should be electrically connected with an external element such as the gate pad, is not anodized. Instead, an interim electrode is formed with a metal such as chromium in order to maintain the contact-resistance in a normal state. This conventional method requires 8 masking steps or processes. The conventional art, which anodizes the aluminum film, will he described below with reference to FIG. 2 and FIGS. 3a-3h.
Aluminum is deposited on a transparent glass substrate 1. A gate bus line 13, a gate pad 15, a gate electrode 11, a short line 19 and a source short connector 27 are formed using a first mask. The short line 19 extends along the edge of the substrate 1 and is connected to each of the gate pads 15. Accordingly, gate elements (the gate electrode, the gate pad, the gate bus line, the short line and the source short connector) have the same electric potential, so that disconnection due to the static electricity, which occurs during the manufacturing process and insulating destruction are prevented. The source short connector 27 will be connected with a source pad in a later step. The source short connector 27 keeps source bus lines at the same electric potential through the short line 19 when the source bus lines are formed (FIGS. 2 and 3a).
The surface of the gate elements is anodized in order to prevent formation of hillocks on the surface thereof. A portion of the gate elements which should be electrically connected with another conductive layer is not anodized by selectively performing the anodization using a photo-resist. The photo-resist is patterned to expose another portion of the gate elements which should be anodized by using a second mask and the anodization step is performed. The patterned photo-resist covers a portion of the gate pad 15 and a portion of the short line 27, both of which will be connected to a source pad and then the anodization process is performed. As a result, an anodized layer 91 is formed on a portion of the aluminum layer as shown in FIG. 3b.
A gate insulating layer 17 is then formed by depositing an insulating material such as SiN.sub.x or SiO.sub.x on the substrate. An intrinsic semiconductor, i.e. amorphous silicon and an impurity doped semiconductor, i.e. doped amorphous silicon, are sequentially deposited. A semiconductor layer 33 and a doped semiconductor layer 35 are formed by patterning the intrinsic semiconductor and impurity doped semiconductor using a third mask (FIGS. 2 and 3c).
A portion of the gate insulating layer 17, which covers the gate pad 15 and the source short connector 27, is removed by using a fourth mask. Then, the gate pad 15 and the source short connector 27 are exposed (FIG. 3d).
Chromium or chromium alloy are deposited on the substrate including the gate insulating layer 17, and patterned to form a source bus line 23, a source electrode 21, a source pad 25, a drain electrode 31 and a gate pad interim electrode 53 by using a fifth mask. The source pad 25 is connected with the source short connector 27 which is exposed through the gate insulating layer 17. Accordingly, all source bus lines 23 are connected with the short line 19, so as to have the same electric potential. The gate pad interim electrode 53 is connected with the gate pad 15 which is exposed through the gate insulating layer 17 (FIGS. 2 and 3e).
A passivation layer 37 is formed by depositing an insulating material, i.e. SiO.sub.x or SiN.sub.x, on the source elements (the source electrode, the drain electrode, the source bus line, the source pad and the gate pad interim electrode). The gate pad interim electrode 53, the source pad 25 and the drain electrode 31 are exposed by patterning the passivation layer 37 using a sixth mask (FIG. 3f).
All of the gate pads 15 and all of the source pads 25 are connected to the short line 19. Therefore, the source pads 25 and the gate pads 15 have the same electric potential during the manufacturing process, so that disconnection of lines due to static electricity and the insulating destruction can be prevented. In the completed LCD product, the lines should not be connected. Instead, the lines should be separated individually. In order to achieve separation of the lines, a portion of the glass substrate 1 on which the short line 19 is located is removed by cutting. Before this cutting step, the signal lines should be tested to determine whether the adjacent lines are shorted and whether each line is disconnected. Generally, this testing step is performed by dividing the lines into an odd-numbered line group and an even-numbered line group, and by applying a voltage to the odd-numbered line group and then to the even-numbered line group, or vice versa. In order to test the lines by using this method, portions of the short line 19, which are squared in FIG. 2, should be removed. In other words, four corners of the short line 19 are cut so that short line 19 is divided into upper, lower, right and left segments. Connecting portions of the even-numbered gate bus lines, which are connected with the left segment of the short line 19, are cut, and connecting portions of the odd-numbered gate bus lines, which are connected with the right segment of the short line 19, are cut. As a result, the gate bus lines 13 are divided into a odd-numbered line group and an even-numbered line group. The source bus lines 23 are also divided into odd-numbered ones and even-numbered ones by using the same method. At this cutting step, connecting portions of the lines which should be cut, depicted by the reference number 93, are etched using a seventh mask (FIGS. 2 and 3g).
Finally, transparent conductive material, i.e. ITO (Indium Tin Oxide), is deposited on the passivation layer 37. A gate pad terminal 57, which is connected with the gate pad interim electrode 53, a source pad terminal 67, which is connected with the source pad 25, and a pixel electrode 41, which is connected with the drain electrode 31, are formed by patterning the ITO using an eighth mask (FIGS. 2 and 3h).
As described above, the gate elements are formed with aluminum, and the formation of hillocks on the surface of the aluminum film is prevented. The problems which result from the aluminum directly contacting the ITO are solved by depositing chromium between the gate pad and the ITO. However, this solution requires additional steps for anodizing the aluminum and cutting the connecting portions of the lines. In addition, this process requires at least eight (8) masking steps or processes. Each masking process, which is used for manufacturing the active panel of the LCD, comprises the steps of rinsing, depositing, baking and etching. Thus, each additional masking step that is required in this process causes the manufacturing time, difficulty and cost to be remarkably increased.